1. Field of Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a dynamic random access semiconductor memory device.
2. Description of Prior Art
In an electrical device at the present, semiconductor memory is one of the most important devices in the electrical device. Please referring to FIG. 1, FIG. 1 is a waveform for reading data from a dynamic random access memory in prior art. The dynamic random access memory is a synchronous dynamic random access memory (SDRAM) and operating according to the system clock XCLK. A clock signal CLKP is fed to a sense amplifier controller of the SDRAM, and the sense amplifier controller generates a signal SAC-SET to enable a data line sense amplifier of the SDRAM. Data signals IO and ION are both transported to an input output sense amplifier through the data line sense amplifier of the SDRAM when the signal SAC-SET is enabled. At the same time, as shown is FIG. 1, the voltage level of the data signal ION is getting lower when the signal SAC-SET is enabled (in logical high level). The input output sense amplifier of the SDRAM compares the voltage levels of the data signals IO and ION, and a sensed data is generated according to the comparison result when a clock signal CLKN is in logical high level.
Please notice here, a timing period for comparing the voltage levels of the data signals IO and ION is negative proportion to the frequency of the system clock XCLK. That is, the voltage drop of the data signal ION may be not enough for providing the input output sense amplifier to sense a correct result before the clock signal CLKN turned to disable (in logical low level). The operating speed of the SDRAM is limited, and the efficiency of a system which the SDRAM belongs to is reduced. Furthermore, there are two data signals IO and ION are needed in the prior art shown in FIG. 1, such as that the area of the circuit is large and the cost of the SDRAM is increased.